US 12,414,326 B2
Thin film transistor featuring variable thickness glue layer with tapered end
Ya-Ling Lee, Hsinchu (TW); Wei-Gang Chiu, New Taipei (TW); Han-Ting Tsai, Kaoshiung (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 17, 2022, as Appl. No. 17/674,811.
Prior Publication US 2023/0261063 A1, Aug. 17, 2023
Int. Cl. H10D 30/67 (2025.01); H01L 21/443 (2006.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01); H10D 99/00 (2025.01)
CPC H10D 30/6729 (2025.01) [H01L 21/443 (2013.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01); H10D 99/00 (2025.01); H10D 30/6755 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a gate electrode disposed over the substrate;
a gate dielectric layer disposed over the gate electrode;
a channel layer disposed over the gate dielectric layer; and
a source electrode and a drain electrode disposed over the channel layer and beside the gate electrode,
wherein each of the source electrode and the drain electrode comprises a glue layer and a metal pattern,
wherein a thickness of the glue layer includes a variable thickness between the metal pattern and the gate dielectric layer, and the thickness of the glue layer is a minimum distance between an inner surface of the glue layer and an outer surface of the glue layer, and
wherein the glue layer between the metal pattern and the gate dielectric layer has a tapered thickness towards the channel layer.