| CPC H10D 30/0415 (2025.01) [H01L 21/0206 (2013.01); H01L 21/02181 (2013.01); H01L 21/02356 (2013.01); H10D 64/017 (2025.01); H10D 64/689 (2025.01)] | 20 Claims |
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1. A semiconductor structure, comprising:
a semiconductor layer disposed over a substrate;
a shallow trench isolation (STI) structure disposed over the substrate and surrounding the semiconductor layer;
gate spacers disposed over the semiconductor layer;
an interfacial layer disposed on the semiconductor layer;
a hafnium-containing dielectric layer of a same and uniform material in its entirety, wherein a first portion of the hafnium-containing dielectric layer having a first thickness is disposed on the interfacial layer and a second portion of the hafnium-containing dielectric layer having a second thickness is disposed along sidewalls of the gate spacers and interfacing side surfaces of a metal gate electrode, and wherein the first thickness is greater than the second thickness;
the metal gate electrode disposed over the hafnium-containing dielectric layer and between the gate spacers; and
source/drain features formed over the semiconductor layer, the source/drain features directly contact side surfaces of the gate spacers, wherein a top surface of the STI structure is below a bottom surface of the source/drain features,
wherein bottom surfaces of the interfacial layer, the second portion of the hafnium-containing dielectric layer, and the gate spacers are substantially coplanar,
wherein the hafnium-containing dielectric layer includes a ferroelectric orthorhombic phase in both the first and second portions of the hafnium-containing dielectric layer, wherein electric dipoles within both the first and second portions of the hafnium-containing dielectric layer are oriented substantially in a same direction parallel to an electric field that is applied when forming the first and second portions of the hafnium-containing dielectric layer.
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