US 12,414,314 B2
Deep trench structure for a capacitive device
En-Shuo Lin, Hsinchu (TW); Sheng Ko, Hsinchu (TW); Chi-Fu Lin, Hsinchu County (TW); Che-Yi Lin, Hsinchu (TW); and Clark Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 28, 2023, as Appl. No. 18/308,702.
Application 18/308,702 is a continuation of application No. 16/949,769, filed on Nov. 13, 2020, granted, now 11,658,206.
Prior Publication US 2023/0268378 A1, Aug. 24, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 1/68 (2025.01); H01G 4/005 (2006.01); H01G 4/35 (2006.01); H01L 23/64 (2006.01)
CPC H10D 1/694 (2025.01) [H01G 4/005 (2013.01); H01G 4/35 (2013.01); H01L 23/642 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming an interlayer dielectric (ILD) layer on a substrate of a capacitive device;
forming a first portion of an intermetal dielectric (IMD) layer on the ILD layer;
forming a second portion of the IMD layer on the first portion of the IMD layer;
forming a metal layer on the second portion of the IMD layer;
etching through the metal layer, through the second portion of the IMD layer, through the first portion of the IMD layer, and partially into the ILD layer to form a plurality of deep trench structures that are partially in the ILD layer;
forming a passivation layer in a bottom and sidewalls of each of the plurality of deep trench structures; and
forming a humidity sensing layer in the plurality of deep trench structures and above the passivation layer,
wherein, in each of the plurality of deep trench structures, a bottom surface of the humidity sensing layer is above a portion of the ILD layer.