US 12,414,311 B2
Integrated circuit with feol resistor
Tien-Chien Huang, Hsinchu (TW); Ruey-Bin Sheen, Hsinchu (TW); and Chih-Hsien Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Feb. 4, 2021, as Appl. No. 17/167,624.
Claims priority of provisional application 63/016,714, filed on Apr. 28, 2020.
Prior Publication US 2021/0335991 A1, Oct. 28, 2021
Int. Cl. H01L 49/02 (2006.01); G06F 30/392 (2020.01); H01L 23/64 (2006.01); H10D 1/47 (2025.01); H10D 89/10 (2025.01)
CPC H10D 1/474 (2025.01) [G06F 30/392 (2020.01); H01L 23/647 (2013.01); H10D 1/47 (2025.01); H10D 89/10 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a resistor circuit comprising:
a dummy transistor comprising a source/drain and a dummy gate, the dummy gate being a first metal resistor strip over a semiconductor substrate, the source/drain being free of a contact, the source/drain including an epitaxial region in the semiconductor substrate, the epitaxial region having a first dopant of a first type, the semiconductor substrate having a second dopant of a second type different from the first type, and
a first metal line and a second metal line extending on a same level height above the first metal resistor strip, wherein both the first metal line and the second metal line overlap and are electrically connected to the first metal resistor strip, wherein at least one of the first metal line or the second metal line is directly over the source/drain; and
a transistor comprising a metal gate strip on a same level height as the first metal resistor strip and extending in parallel with the first metal resistor strip.