| CPC H10B 80/00 (2023.02) [G11C 16/0483 (2013.01); G11C 16/16 (2013.01); G11C 16/3445 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] | 20 Claims |
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1. A semiconductor memory device, comprising:
a peripheral circuit structure comprising a circuit board, a peripheral circuit on the circuit board, a first insulating layer partially covering the peripheral circuit, and a plurality of first bonding pads on the first insulating layer;
a first cell array structure comprising a first memory cell array, a first conductive plate structure on the first memory cell array, a second insulating layer partially covering the first memory cell array, a plurality of second bonding pads on the second insulating layer, and a plurality of third bonding pads on the second insulating layer; and
a second cell array structure stacked on the first cell array structure, and comprising a second memory cell array, a second conductive plate structure on the second memory cell array, a third insulating layer partially covering the second memory cell array, and a plurality of fourth bonding pads on the third insulating layer,
wherein the first cell array structure and the second cell array structure are sequentially stacked in a vertical direction on the peripheral circuit structure,
wherein the plurality of first bonding pads respectively contact the plurality of second bonding pads,
wherein the plurality of third bonding pads respectively contact the plurality of fourth bonding pads,
wherein the first memory cell array comprises:
a plurality of first wordlines; and
a first stepped structure in which a first planar area of the first stepped structure gradually decreases as a first distance from the first conductive plate structure increases,
wherein the second memory cell array comprises:
a plurality of second wordlines; and
a second stepped structure in which a second planar area of the second stepped structure gradually decreases as a second distance from the second conductive plate structure increases,
wherein the first cell array structure further comprises a first wordline contact coupled to a first wordline of the plurality of first wordlines of the first memory cell array,
wherein the second cell array structure further comprises a second wordline contact coupled to a second wordline of the plurality of second wordlines of the second memory cell array, and
wherein the first wordline contact is electrically coupled to the second wordline contact.
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