US 12,414,306 B2
Method of fabricating memory devices using pocket integration
Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Niloy Mukherjee, San Ramon, CA (US); Amrita Mathuriya, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/485,147.
Application 17/485,147 is a continuation of application No. 17/465,792, filed on Sep. 2, 2021, granted, now 12,069,866.
Prior Publication US 2023/0077054 A1, Mar. 9, 2023
Int. Cl. H10B 53/30 (2023.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H10B 53/10 (2023.01); H01L 23/532 (2006.01); H10D 1/68 (2025.01)
CPC H10B 53/30 (2023.02) [H01L 21/76802 (2013.01); H01L 23/528 (2013.01); H01L 23/535 (2013.01); H10B 53/10 (2023.02); H01L 23/53209 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01); H10D 1/682 (2025.01); H10D 1/694 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A method of fabricating a device structure, the method comprising:
forming a first conductive interconnect in a dielectric in a memory region and a second conductive interconnect in a logic region;
depositing an etch stop layer on the dielectric and on the first conductive interconnect and on the second conductive interconnect;
etching and removing the etch stop layer from the memory region but not from the logic region;
depositing a material layer stack including a non-linear polar material on the first conductive interconnect, on the dielectric, on a sidewall of the etch stop layer, at an interface between the memory region and the logic region and on the etch stop layer;
forming a memory device by etching the material layer stack, wherein the etching forms the memory device directly on at least a portion of the first conductive interconnect;
depositing an encapsulation layer on the memory device, including on a top surface and on at least a sidewall of the memory device;
forming a mask on the encapsulation layer above the memory device;
using the mask to etch portions of the encapsulation layer;
blanket depositing a dielectric layer;
forming a first opening in the dielectric layer, the first opening exposing the second conductive interconnect in the logic region;
forming an interconnect via in the first opening and a metal line on the interconnect via by depositing a conductive material in the first opening;
forming a second opening in the dielectric layer and in the encapsulation layer, the second opening exposing the memory device; and
forming a via electrode in the second opening by depositing the conductive material in the second opening.