US 12,414,304 B2
3D monolithic stacking memory structure with oxide-semiconductor field effect transistor and ferroelectric metal-insulator-metal storage capacitor
Shou-Zen Chang, Hsinchu (TW); Ming-Han Liao, Hsinchu (TW); Min-Cheng Chen, Hsinchu County (TW); and Hiroshi Yoshida, Hsinchu (TW)
Assigned to Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed by Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed on Mar. 10, 2022, as Appl. No. 17/692,135.
Claims priority of application No. 110144430 (TW), filed on Nov. 29, 2021.
Prior Publication US 2023/0171966 A1, Jun. 1, 2023
Int. Cl. H10B 51/20 (2023.01); G11C 11/22 (2006.01); H01L 23/528 (2006.01); H10D 30/67 (2025.01)
CPC H10B 51/20 (2023.02) [G11C 11/221 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); H01L 23/5283 (2013.01); H10D 30/6755 (2025.01)] 9 Claims
OG exemplary drawing
 
1. A 3D monolithic stacking memory structure, comprising:
a semiconductor substrate;
a field effect transistor (FET) on said semiconductor substrate;
a back-end-of-line (BEOL) interconnect on said field effect transistor and said semiconductor substrate, and said BEOL interconnect comprises multiple BEOL metal layers, inter-metal dielectrics and vias;
an oxide-semiconductor field effect transistor (OSFET) in said BEOL interconnect, wherein a drain of said OSFET connects with a gate of said FET, and said drain and a source of said OSFET are parts of said BEOL metal layers; and
a ferroelectric metal-insulator-metal (FEMIM) storage capacitor formed on top of said BEOL interconnect, wherein said FEMIM storage capacitor with high capacitance provides multilevel storage states in read operation of said 3D monolithic stacking memory structure, and said FEMIM storage capacitor comprises a capacitive dielectric layer set between a top electrode and a bottom electrode, and said bottom electrode is one of said multiple vias extending through said inter-metal dielectrics of said BEOL interconnect, and said capacitive dielectric layer is in a shape of inverted-U directly encapsulating on parts of a sidewall of said bottom electrode, and said top electrode formed on said capacitive dielectric layer is a top metal layer of said multiple BEOL metal layers, and said bottom electrode connects with said drain of said OSFET and said gate of said FET, wherein said FET, said OSFET and said FEMIM storage capacitor are set sequentially from bottom to top on said semiconductor substrate.