US 12,414,293 B2
Antifuse-type one time programming memory with forksheet transistors
Lun-Chun Chen, Hsinchu County (TW); and Ping-Lung Ho, Hsinchu County (TW)
Assigned to EMEMORY TECHNOLOGY INC., Hsin-Chu (TW)
Filed by eMemory Technology Inc., Hsin-Chu (TW)
Filed on Jan. 16, 2024, as Appl. No. 18/413,085.
Claims priority of provisional application 63/453,182, filed on Mar. 20, 2023.
Prior Publication US 2024/0324191 A1, Sep. 26, 2024
Int. Cl. H10B 20/00 (2023.01); G11C 17/16 (2006.01); H10B 20/25 (2023.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01)
CPC H10B 20/25 (2023.02) [G11C 17/165 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01)] 28 Claims
OG exemplary drawing
 
1. An antifuse-type one time programming memory comprising a first memory cell, the first memory cell comprising:
a semiconductor substrate;
an isolation wall inserted in the semiconductor substrate;
a first nanowire, wherein a first-portion surface of the first nanowire is contacted with a first side of the isolation wall;
a first gate structure contacted with a second-portion surface of the first nanowire, and comprising a first spacer, a second spacer, a first gate dielectric layer and a first gate layer, wherein the first gate layer is electrically connected with an antifuse control line, the first gate dielectric layer is contacted with a central region of the first nanowire, the first gate layer is contacted with the first gate dielectric layer, and the first gate layer is located over the semiconductor substrate, wherein a first terminal of the first nanowire is contacted with the first spacer and supported by the first spacer, a second terminal of the first nanowire is contacted with the second spacer and supported by the second spacer, and the first spacer and the second spacer are formed over the semiconductor substrate;
a first drain/source structure formed over the semiconductor substrate and electrically contacted with the first terminal of the first nanowire;
a second drain/source structure formed over the semiconductor substrate and electrically contacted with the second terminal of the first nanowire, wherein the first nanowire, the first gate structure, the first drain/source structure and the second drain/source structure are collaboratively formed as a first antifuse transistor, and the first antifuse transistor is a forksheet transistor; and
a first select transistor, wherein a first drain/source terminal of the first select transistor is electrically connected with the second drain/source structure of the first antifuse transistor, a gate terminal of the first select transistor is electrically connected with a word line, and a second drain/source terminal of the first select transistor is electrically connected with a first bit line.