| CPC H10B 12/05 (2023.02) [H10B 12/315 (2023.02); H10B 12/482 (2023.02)] | 16 Claims |
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1. A semiconductor structure, comprising:
a substrate, the substrate being provided with a plurality of semiconductor pillars arranged at intervals, the plurality of semiconductor pillars comprising a first doped region, a channel region and a second doped region sequentially arranged along a direction distant from a surface of the substrate; and
a plurality of word lines extending along a first direction and an insulating layer between adjacent two of the plurality of word lines, each of the plurality of word lines surrounding the channel region of the plurality of semiconductor pillars arranged along the first direction, and along the direction distant from the surface of the substrate, a width of the insulating layer perpendicular to the first direction gradually decreasing;
a plurality of dielectric layers extending along the first direction, the plurality of dielectric layers surrounding the first doped region of the plurality of semiconductor pillars arranged along the first direction, and the plurality of word lines being positioned on top surfaces of the plurality of dielectric layers, and the insulating layer being further positioned between adjacent two of the plurality of dielectric layers.
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