US 12,414,243 B2
Manufacturing method of package structure
Kai-Ming Yang, Hsinchu County (TW); Chen-Hao Lin, Keelung (TW); Cheng-Ta Ko, Taipei (TW); John Hon-Shing Lau, New Territories (HK); Yu-Hua Chen, Hsinchu (TW); and Tzyy-Jang Tseng, Hsinchu (TW)
Assigned to Unimicron Technology Corp., Taoyuan (TW)
Filed by Unimicron Technology Corp., Taoyuan (TW)
Filed on Aug. 8, 2022, as Appl. No. 17/818,006.
Application 17/818,006 is a division of application No. 16/379,816, filed on Apr. 10, 2019, granted, now 11,445,617.
Application 14/602,656 is a division of application No. 13/604,968, filed on Sep. 6, 2012, granted, now 8,946,564, issued on Feb. 3, 2015.
Application 16/379,816 is a continuation in part of application No. 15/701,435, filed on Sep. 11, 2017, abandoned.
Application 15/701,435 is a continuation in part of application No. 15/391,861, filed on Dec. 28, 2016, granted, now 11,127,664, issued on Sep. 21, 2021.
Application 15/391,861 is a continuation in part of application No. 14/602,656, filed on Jan. 22, 2015, granted, now 9,781,843, issued on Oct. 3, 2017.
Claims priority of application No. 100139667 (TW), filed on Oct. 31, 2011; application No. 105133848 (TW), filed on Oct. 20, 2016; application No. 106123710 (TW), filed on Jul. 14, 2017; and application No. 107112303 (TW), filed on Apr. 10, 2018.
Prior Publication US 2022/0375919 A1, Nov. 24, 2022
Int. Cl. H05K 3/40 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/15 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H05K 1/11 (2006.01); H05K 1/14 (2006.01); H05K 1/18 (2006.01); H05K 3/32 (2006.01); H05K 3/46 (2006.01)
CPC H05K 3/4038 (2013.01) [H01L 21/4846 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/76898 (2013.01); H01L 23/145 (2013.01); H01L 23/147 (2013.01); H01L 23/15 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 24/83 (2013.01); H01L 25/50 (2013.01); H05K 1/11 (2013.01); H05K 1/112 (2013.01); H05K 1/142 (2013.01); H05K 1/183 (2013.01); H05K 3/32 (2013.01); H05K 3/4682 (2013.01); H01L 23/49816 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/8385 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/014 (2013.01); H01L 2924/15311 (2013.01); H05K 1/185 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/1469 (2013.01); Y10T 29/4913 (2015.01); Y10T 29/49146 (2015.01); Y10T 29/49165 (2015.01)] 10 Claims
OG exemplary drawing
 
1. A method of manufacturing package structure, comprising steps of:
providing a carrier board comprising a supporting layer, a first release layer, a second release layer and a plurality of metal layers, the first release layer and the second release layer are disposed on opposite surfaces of the supporting layer respectively, and the metal layers are disposed on the first release layer and the second release layer;
forming an insulating composite layer on at least one of the metal layers;
disposing a chip packaging module on at least one of the insulating composite layers, the chip packaging module comprising a sealant and a first chip embedded therein, wherein the first chip has a plurality of first conductive pads, the first conductive pads are exposed through the sealant;
forming a first circuit layer module on the chip packaging module, wherein the first circuit layer module comprises at least one first dielectric layer and at least one first circuit layer, the first dielectric layer has a plurality of first conductive vias, the first circuit layer is located on the first dielectric layer, in contact with the first conductive vias, and electrically connected to the first conductive pads through the first conductive vias;
disposing a second chip on at least one of the first circuit layer modules, the second chip having a plurality of second conductive pads;
forming a second circuit layer module on at least one of the first circuit layer modules and the second chip, wherein the second circuit layer module comprises at least one second dielectric layer and at least one second circuit layers, the second dielectric layer having a plurality of second conductive vias, the second circuit layer is located on the second dielectric layer, in contact with the second conductive vias, and electrically connected to the second conductive pads through the second conductive vias; and
forming a protecting layer on at least one of the second circuit layer modules, wherein the protecting layer has a plurality of openings exposing a portion of the second circuit layer module.