US 12,414,238 B2
Substrate structures and methods of manufacture
Yusheng Lin, Phoenix, AZ (US); and Sadamichi Takakusaki, Ota (JP)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Jul. 29, 2022, as Appl. No. 17/816,144.
Application 17/816,144 is a division of application No. 15/868,747, filed on Jan. 11, 2018, granted, now 11,419,217.
Application 15/868,747 is a division of application No. 15/206,574, filed on Jul. 11, 2016, granted, now 9,883,595, issued on Jan. 30, 2018.
Application 15/206,574 is a division of application No. 14/534,482, filed on Nov. 6, 2014, granted, now 9,408,301, issued on Aug. 2, 2016.
Prior Publication US 2022/0369468 A1, Nov. 17, 2022
Int. Cl. H05K 3/06 (2006.01); C04B 37/02 (2006.01); H01L 21/48 (2006.01); H01L 23/14 (2006.01); H01L 23/15 (2006.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01); H05K 1/03 (2006.01); H05K 1/05 (2006.01); H05K 1/09 (2006.01); H05K 3/00 (2006.01); H05K 3/20 (2006.01); H05K 3/46 (2006.01)
CPC H05K 3/06 (2013.01) [C04B 37/021 (2013.01); H01L 21/4807 (2013.01); H01L 21/4857 (2013.01); H01L 21/4871 (2013.01); H01L 23/142 (2013.01); H01L 23/15 (2013.01); H01L 23/3735 (2013.01); H05K 1/0306 (2013.01); H05K 1/0313 (2013.01); H05K 1/036 (2013.01); H05K 1/056 (2013.01); H05K 1/09 (2013.01); H05K 3/0011 (2013.01); H05K 3/064 (2013.01); H05K 3/4644 (2013.01); C04B 2237/34 (2013.01); C04B 2237/343 (2013.01); C04B 2237/402 (2013.01); C04B 2237/406 (2013.01); C04B 2237/407 (2013.01); C04B 2237/52 (2013.01); C04B 2237/64 (2013.01); C04B 2237/82 (2013.01); H01L 23/49822 (2013.01); H01L 2924/0002 (2013.01); H05K 3/0058 (2013.01); H05K 3/0064 (2013.01); H05K 3/0067 (2013.01); H05K 3/20 (2013.01); H05K 3/202 (2013.01); H05K 2201/09736 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A power electronic substrate, comprising:
a plurality of copper traces coupled to a first dielectric layer, wherein the plurality of copper traces comprise a first thickness and a second thickness measured perpendicularly to the first dielectric layer;
a ceramic layer comprising a first side and a second side, wherein the first side of the ceramic layer is coupled to the first dielectric layer;
a second dielectric layer coupled to the second side of the ceramic layer; and
a metallic baseplate coupled to the second dielectric layer;
wherein the ceramic layer comprises two different thicknesses, a first surface of the ceramic layer comprising a step therein;
wherein the first dielectric layer covers a first portion of the first surface of the ceramic layer and a second portion of the first surface of the ceramic layer; and
wherein the step in the first surface separates the first portion from the second portion.