US 12,414,229 B2
Tearing security feature of printed circuit substrates
Arthur J. Higby, Cottekill, NY (US); David Clifford Long, Wappingers Falls, NY (US); James Busby, New Paltz, NY (US); William Santiago-Fernandez, Hopewell Junction, NY (US); John R. Dangler, Rochester, MN (US); Russell A. Budd, North Salem, NY (US); Philipp K Buchling Rego, Wappingers Falls, NY (US); Hannah Wendling, Poughquag, NY (US); and Lauren Boston, Poughkeepsie, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Oct. 10, 2022, as Appl. No. 17/963,138.
Prior Publication US 2024/0121890 A1, Apr. 11, 2024
Int. Cl. H05K 1/02 (2006.01); H05K 1/18 (2006.01); H05K 5/02 (2006.01)
CPC H05K 1/0275 (2013.01) [H05K 1/0292 (2013.01); H05K 1/181 (2013.01); H05K 5/0208 (2013.01); H05K 2201/0909 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A structure comprising:
a circuitry substrate including a least one of a top tamper enclosure and a bottom tamper enclosure;
a connection bonding the at least one of the top tamper enclosure and the bottom tamper enclosure to the circuitry substrate; and
a tear initiation site extending along at least a portion of a perimeter of a protected area of the circuitry substrate that includes the at least one of the top tamper enclosure and the bottom tamper enclosure, wherein the tear initiation site is located and configured to enable propagation of a delamination of at least one internal layer of the circuitry substrate and a severing of a security circuit when a removal force is applied to the at least one of the top tamper enclosure and the bottom tamper enclosure and includes a change of dielectric material having a reduced bond strength to other layers of the circuitry substrate.