US 12,413,870 B2
Solid-state imaging element
LuongHung Asakura, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 18/550,180
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Jan. 13, 2022, PCT No. PCT/JP2022/000864
§ 371(c)(1), (2) Date Sep. 12, 2023,
PCT Pub. No. WO2022/190657, PCT Pub. Date Sep. 22, 2022.
Claims priority of application No. 2021-045378 (JP), filed on Mar. 19, 2021.
Prior Publication US 2024/0187752 A1, Jun. 6, 2024
Int. Cl. H04N 25/616 (2023.01); H04N 25/532 (2023.01); H04N 25/766 (2023.01); H04N 25/77 (2023.01); H04N 25/78 (2023.01)
CPC H04N 25/616 (2023.01) [H04N 25/532 (2023.01); H04N 25/766 (2023.01); H04N 25/77 (2023.01); H04N 25/78 (2023.01)] 20 Claims
OG exemplary drawing
 
1. A solid-state imaging element comprising:
a predetermined number of capacitive elements;
a pre-stage circuit that generates a predetermined reset level and a signal level corresponding to an exposure amount and causes each of the capacitive elements to hold a corresponding one of the reset level and the signal level;
a selection circuit in which a selection transistor that opens and closes a path between one end of each of the capacitive elements and a predetermined node is arranged;
a post-stage circuit that sequentially reads the reset level and the signal level via the node; and
a vertical scanning circuit that performs control to lower a potential of the one end when the reset level and the signal level are held.