| CPC H04N 19/96 (2014.11) [H04N 19/176 (2014.11); H04N 19/184 (2014.11); H04N 19/70 (2014.11)] | 3 Claims |

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1. A video signal decoding apparatus, comprising a processor,
wherein the processor is configured to:
parse a first parameter, wherein the first parameter indicates whether a skip mode is applied to a current block;
parse a second parameter, when the first parameter indicates the skip mode is not applied to the current block, wherein the second parameter indicates whether a merge mode is applied to the current block; and
parse a third parameter, when the first parameter indicates the skip mode is not applied to the current block and the second parameter indicates that the merge mode is not applied to the current block, wherein the third parameter indicates whether a syntax structure regarding transformation is present for a coding unit related to the current block,
wherein when the first parameter indicates that the skip mode is applied to the current block, the third parameter is not parsed, and a value of the third parameter is inferred as a first value indicating that the syntax structure regarding transformation is not present for the coding unit related to the current block,
wherein when the first parameter indicates that the skip mode is not applied to the current block and the second parameter indicates that the merge mode is applied to the current block, the third parameter is not parsed and the value of the third parameter is inferred as a second value indicating that the syntax structure regarding transformation is present for the coding unit related to the current block.
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