| CPC H04N 19/105 (2014.11) [H04N 19/132 (2014.11); H04N 19/159 (2014.11); H04N 19/176 (2014.11); H04N 19/46 (2014.11); H04N 19/82 (2014.11)] | 4 Claims |

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1. A video signal decoding device comprising a processor,
wherein the processor is configured to:
when a prediction mode of a current block is an intra-prediction mode, obtain, from a bitstream, an ISP (Intra Sub Partitions) mode flag indicating whether to apply an ISP mode to the current block, and determine whether to apply the ISP mode to the current block according to the ISP mode flag;
generate a reference sample for the current block;
determine a value of a filter flag for specifying an interpolation filter applied to the reference sample, wherein the interpolation filter includes a plurality of filter coefficients;
generate a prediction sample of the current block by performing filtering for the reference sample by using the interpolation filter specified by the value of the filter flag; and
reconstruct the current block on the basis of the prediction sample,
wherein when it is determined that the ISP mode is applied on the current block, the value of the filter flag is determined to be a first value among a plurality of values, and
wherein when it is determined that the ISP mode is not applied on the current block, the value of the filter flag is determined to be any one among the plurality of values based on a size of the current block,
wherein the ISP mode flag is obtained based on which reference line is used among multiple reference lines.
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