| CPC H04L 65/80 (2013.01) [H04L 65/403 (2013.01); H04L 65/70 (2022.05); H04L 65/75 (2022.05); H04N 19/13 (2014.11); H04N 19/176 (2014.11); H04N 19/184 (2014.11); H04N 19/70 (2014.11)] | 3 Claims |

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1. An encoder comprising:
circuitry; and
memory connected to the circuitry,
wherein the circuitry, in operation:
determines whether to apply arithmetic encoding to binary data of coefficient information of an image block, the binary data being obtained by binarizing the coefficient information, the coefficient information being derived from prediction residuals of the image block;
in a first case where it is determined that the arithmetic encoding is to be applied and a number of Context-based Adaptive Binary Arithmetic Coding (CABAC) processes is within an allowable range, encodes the coefficient information according to a first syntax and outputs a first bitstream including the encoded coefficient information; and
in a second case where it is determined that the arithmetic encoding is not to be applied, subtracts 1 from a value of an initial non-zero coefficient to obtain an intermediate value, encodes the intermediate value according to a second syntax different from the first syntax and outputs a second bitstream that includes the encoded intermediate value, wherein a coding amount is smaller in the second case than the first case.
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