US 12,413,539 B2
Switch-managed resource allocation and software execution
Patrick Connor, Beaverton, OR (US); James R. Hearn, Hillsboro, OR (US); Kevin Liedtke, Portland, OR (US); and Scott P. Dubal, Oregon City, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 10, 2024, as Appl. No. 18/768,909.
Application 18/768,909 is a continuation of application No. 16/905,761, filed on Jun. 18, 2020, abandoned.
Prior Publication US 2024/0364641 A1, Oct. 31, 2024
Int. Cl. H04L 49/356 (2022.01); G06F 9/455 (2018.01); H04L 47/125 (2022.01); H04L 47/32 (2022.01); H04L 67/1097 (2022.01); H04L 69/22 (2022.01)
CPC H04L 49/356 (2013.01) [G06F 9/45558 (2013.01); H04L 47/125 (2013.01); H04L 47/32 (2013.01); H04L 67/1097 (2013.01); H04L 69/22 (2013.01); G06F 2009/4557 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45595 (2013.01)] 35 Claims
OG exemplary drawing
 
1. A packaged integrated circuit, the packaged integrated circuit being configurable to be used in switching operations in association with at least one network, multiple graphics processing units (GPUs), multiple compute express link (CXL).mem memory devices, and multiple central processing units (CPUs), the packaged integrated circuit comprising:
interface circuitry to be communicatively coupled to the at least one network, the multiple GPUs, the multiple CXL.mem memory devices, and the multiple CPUs; and
switch circuitry to implement the switching operations in association with respective data communication processing, the switching operations to be carried out via the interface circuitry in association with the at least one network, the multiple GPUs, the multiple CXL.mem devices, and the multiple CPUs;
wherein:
the multiple CXL.mem devices are to be in a pooled configuration;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the at least one network in accordance with remote direct memory access (RDMA) over Converged Ethernet (RoCE) protocol;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple GPUs and the multiple CPUs in accordance with peripheral component interconnect express (PCIe) protocol;
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple CXL.mem memory devices in accordance with CXL protocol;
the switch circuitry is to implement the switching operations and/or the respective data communication processing in association with compute and/or accelerator resource aggregation and/or compute and/or accelerator resource composition;
the switching operations and/or the respective communication processing are software programmable, at least in part; and
the switch circuitry is to carry out, at least in part, the respective data communication processing that is in association with the multiple CXL.mem memory devices in association with memory page data transfer.