| CPC H04L 47/56 (2013.01) [H04L 43/087 (2013.01)] | 14 Claims |
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1. A packet control system comprising at least one processor, the at least one processor carrying out:
an acquisition process of acquiring a packet associated with a delay jitter which is requested;
an enqueuing process of enqueuing the packet into a queue, among a plurality of queues, at a level which corresponds to the delay jitter associated with the packet, wherein the plurality of queues are classified into levels respectively corresponding to different delay jitters; and
a dequeuing process of dequeuing, in accordance with a dequeue timing specified for the queue, the packet which has been enqueued into the queue at the level corresponding to the delay jitter associated with the packet, and sending the packet which has been dequeued to a network,
wherein:
in the enqueuing process, the at least one processor reenqueues a packet which has been dequeued from a queue at a second level into a queue at a first level that corresponds to the delay jitter associated with the packet, the second level being different from the first level;
the plurality of queues are classified into levels such that delay granularity is greater as the level increases;
in the acquisition process, the at least one processor acquires the packet that is associated with a sending timing which is requested and with the delay jitter;
in the enqueuing process,
the at least one processor enqueues the packet acquired in the acquisition process into a queue corresponding to the sending timing associated with the packet, and
the at least one processor enqueues a packet which has been dequeued from a queue at the second level into a queue at a level that is one level below the second level, the second level being higher than the first level.
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