US 12,413,481 B2
Data center networks using bottleneck structures
Jordi Ros-Giralt, Vilafranca del Penedes (ES); Noah Amsel, New York, NY (US); and Richard Lethin, Bronxville, NY (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM INCORPORATED, San Diego, CA (US)
Filed on May 2, 2024, as Appl. No. 18/653,829.
Application 18/653,829 is a continuation of application No. 17/554,457, filed on Dec. 17, 2021, granted, now 12,218,802.
Claims priority of provisional application 63/150,305, filed on Feb. 17, 2021.
Prior Publication US 2024/0291722 A1, Aug. 29, 2024
Int. Cl. H04L 41/14 (2022.01); H04L 47/127 (2022.01); H04L 49/1515 (2022.01)
CPC H04L 41/145 (2013.01) [H04L 47/127 (2013.01); H04L 49/1515 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A processor-implemented method for selecting a network parameter, the method comprising:
obtaining an expected traffic pattern for a network, the network comprising a plurality of levels of switches and corresponding links;
selecting a network parameter corresponding to a switch or link at a selected level based on, in part, a portion of the expected network traffic pattern associated with that switch or link; and
calculating a wasteless network design, based on the network parameter, that minimizes flow completion times and maximizes network throughput, the wasteless network design configured to route the expected traffic pattern with all bandwidth of each link used throughout transmission of the expected traffic pattern.