| CPC H04L 25/03057 (2013.01) [H04B 1/76 (2013.01)] | 20 Claims |

|
1. An equalizer circuit comprising:
an analog front end circuit configured to receive an analog input signal from a transmission line;
an analog finite impulse response filter circuit comprising:
a sample and hold circuit configured to sample an output of the analog front end circuit; and
a weighting circuit configured to weight the output of the analog front end circuit to generate a feedforward signal;
a decision feedback equalizer circuit configured to receive an output of the analog front end circuit and the feedforward signal; and
a first input port for receiving a coefficient for a first tap, the weighting circuit of the analog finite impulse response filter circuit being configured to weight the output of the analog front end circuit based on the coefficient for the first tap.
|