| CPC H04L 5/0005 (2013.01) [H04L 1/0045 (2013.01); H04L 1/0047 (2013.01); H04L 1/0072 (2013.01); H04L 5/0023 (2013.01); H04L 5/0044 (2013.01); H04L 5/0091 (2013.01); H04L 25/0238 (2013.01); H04L 25/0258 (2013.01); H04L 27/0014 (2013.01); H04L 27/2676 (2013.01); H04L 5/0053 (2013.01); H04L 2027/0026 (2013.01)] | 20 Claims |

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1. An apparatus, comprising:
one or more memories storing processor-executable code; and
one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the apparatus to:
receive a first control message comprising an indication of a plurality of resources allocated for a semi-persistently scheduled (SPS) physical downlink shared channel (PDSCH) and an indication of a first transmission configuration indication (TCI) state;
receive configuration information for a control channel search space set, the configuration information comprising an indication of an absence of a physical downlink control channel (PDCCH) transmission in the control channel search space set; and
receive a transmission associated with the SPS PDSCH in a resource of the plurality of resources using a beam associated with a second TCI state, the second TCI state being associated with a control resource set (CORESET) associated with the control channel search space set.
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