US 12,413,304 B2
Power calibration and monitoring system
Achal Venkatesh, Bangalore (IN); and Birama Goumballa, Larra (FR)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Feb. 10, 2023, as Appl. No. 18/167,136.
Claims priority of application No. 202221072348 (IN), filed on Dec. 14, 2022.
Prior Publication US 2024/0204870 A1, Jun. 20, 2024
Int. Cl. H03M 1/66 (2006.01); H03F 3/20 (2006.01); H04B 10/079 (2013.01)
CPC H04B 10/07955 (2013.01) [H03F 3/20 (2013.01); H03M 1/66 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a functional circuit configured to generate a differential pair of node voltages; and
a power calibration and monitoring system comprising:
a digital-to-analog converter (DAC) configured to generate a differential pair of feedback currents based on a digital count;
a variable gain amplifier (VGA) that is coupled to the DAC in a negative feedback configuration, and configured to generate a differential pair of amplified signals based on a magnitude difference between (i) the differential pair of feedback currents and (ii) a differential pair of detection currents that is derived from the differential pair of node voltages;
a counter configured to generate the digital count based on the differential pair of amplified signals, wherein the differential pair of feedback currents is controlled based on the digital count such that the magnitude difference between the differential pair of detection currents and the differential pair of feedback currents is within a first tolerance limit, and wherein based on the digital count, a power associated with the functional circuit is at least one of calibrated and monitored; and
a filter that is coupled to the counter, the filter configured to receive the digital count for a plurality of clock cycles associated with the counter and generate a control code based on the digital count of the plurality of clock cycles.