US 12,413,251 B2
Semiconductor memory device and method of controlling the same
Shinichi Kanno, Tokyo (JP); and Hironori Uchikawa, Yokohama Kanagawa (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jul. 12, 2024, as Appl. No. 18/771,866.
Application 13/757,935 is a division of application No. 13/465,624, filed on May 7, 2012, granted, now 8,386,881, issued on Feb. 26, 2013.
Application 18/771,866 is a continuation of application No. 18/148,060, filed on Dec. 29, 2022, granted, now 12,074,616.
Application 18/148,060 is a continuation of application No. 17/317,280, filed on May 11, 2021, granted, now 11,575,395, issued on Feb. 7, 2023.
Application 17/317,280 is a continuation of application No. 16/357,696, filed on Mar. 19, 2019, granted, now 11,038,536, issued on Jun. 15, 2021.
Application 16/357,696 is a continuation of application No. 15/421,746, filed on Feb. 1, 2017, abandoned.
Application 15/421,746 is a continuation of application No. 14/920,510, filed on Oct. 22, 2015, abandoned.
Application 14/920,510 is a continuation of application No. 14/601,664, filed on Jan. 21, 2015, granted, now 9,384,090, issued on Jul. 5, 2016.
Application 14/601,664 is a continuation of application No. 14/231,140, filed on Mar. 31, 2014, granted, now 8,959,411, issued on Feb. 17, 2015.
Application 14/231,140 is a continuation of application No. 13/757,935, filed on Feb. 4, 2013, granted, now 8,732,544, issued on May 20, 2014.
Application 13/465,624 is a continuation of application No. 13/090,539, filed on Apr. 20, 2011, granted, now 8,196,008, issued on Jun. 15, 2012.
Application 13/090,539 is a continuation of application No. 12/404,861, filed on Mar. 16, 2009, granted, now 8,117,517, issued on Feb. 14, 2012.
Application 12/404,861 is a continuation of application No. PCT/JP2008/063344, filed on Jul. 17, 2008.
Claims priority of application No. 2007-225996 (JP), filed on Aug. 31, 2007.
Prior Publication US 2024/0372567 A1, Nov. 7, 2024
Int. Cl. H03M 13/29 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G11C 29/52 (2006.01); H03M 13/00 (2006.01); H03M 13/03 (2006.01); H03M 13/35 (2006.01)
CPC H03M 13/2906 (2013.01) [G06F 11/10 (2013.01); G06F 11/1004 (2013.01); G06F 11/1008 (2013.01); G06F 11/1068 (2013.01); G06F 13/1673 (2013.01); G06F 13/4068 (2013.01); G11C 29/52 (2013.01); H03M 13/29 (2013.01); H03M 13/35 (2013.01); H03M 13/6561 (2013.01); H03M 13/03 (2013.01); Y02D 10/00 (2018.01)] 31 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a flash memory including a plurality of memory cells, each of the plurality of memory cells being configured to store data in accordance with a threshold voltage thereof; and
a circuit electrically connected to the flash memory and configured to:
generate a plurality of error detection codes to detect an error in a plurality of first data items, respectively;
generate a plurality of second data items to restore a plurality of first data blocks when the plurality of first data blocks are read from the flash memory, respectively, each of the plurality of first data blocks including one of the plurality of first data items and one of the plurality of error detection codes corresponding thereto;
generate a third data item to restore a second data block when the second data block is read from the flash memory, the second data block including at least a part of each of the plurality of first data blocks; and
write the plurality of first data blocks, the plurality of second data items, and the third data item into the flash memory such that each of the plurality of memory cells stores data having a plurality of bits.