| CPC H03M 3/426 (2013.01) [H03M 1/0854 (2013.01); H03M 1/16 (2013.01); H03M 3/498 (2013.01)] | 20 Claims |

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1. An apparatus comprising:
a reconfigurable analog-to-digital converter (ADC), the reconfigurable ADC configured to selectively support at least two different resolution settings, the reconfigurable ADC including:
a successive-approximation-register (SAR) ADC, the SAR ADC configured to:
perform a first cycle of an N-bit analog-to-digital conversion of an analog input voltage to generate an N-bit digital output, the N-bit analog-to-digital conversion including a conversion noise and a residual voltage after the first cycle of the N-bit analog-to-digital conversion; and
amplify a difference in the analog input voltage between two close time intervals;
a noise-canceling circuit configured to lower the conversion noise by sampling the analog input voltage after amplifying the difference in the analog input voltage; and
a noise-shaping circuit configured to add or subtract the residual voltage from the first cycle to a second cycle of the N-bit analog-to-digital conversion to reduce a quantization noise of the second cycle of the N-bit analog-to-digital conversion, the reconfigurable ADC being configured to selectively operate in one of at least two different modes of operation that comprise at least two of:
a first mode of operation, the first mode of operation configured to use the SAR ADC, the noise-canceling circuit, and the noise-shaping circuit;
a second mode of operation, the second mode of operation configured to use the SAR ADC and the noise-canceling circuit;
a third mode of operation, the third mode of operation configured to use the SAR ADC and the noise-canceling circuit; and
a fourth mode of operation, the fourth mode of operation configured to use the SAR ADC.
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