US 12,413,237 B2
Charge-injection SAR ADC for correcting full scale PVT variation
Yuan-Ju Chao, Cupertino, CA (US); John H Yu, San Jose, CA (US); and Krishnamurthy Subramanian, Saratoga, CA (US)
Assigned to PIMIC, Inc., Cupertino, CA (US)
Filed by Yuan-Ju Chao, Cupertino, CA (US); John H Yu, San Jose, CA (US); and Krishnamurthy Subramanian, Saratoga, CA (US)
Filed on Jan. 9, 2024, as Appl. No. 18/407,613.
Claims priority of provisional application 63/438,040, filed on Jan. 10, 2023.
Prior Publication US 2024/0235565 A1, Jul. 11, 2024
Int. Cl. H03M 1/06 (2006.01); H03M 1/18 (2006.01); H03M 1/46 (2006.01)
CPC H03M 1/0604 (2013.01) [H03M 1/18 (2013.01); H03M 1/462 (2013.01); H03M 1/466 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A power, voltage, temperature (PVT) variation corrected charge-injection SAR ADC, comprising:
a charge-injection circuit (CIC) having matching first (M0) and second (M1) transistors that are in a cascode relationship with respect to matching third (M3) and a fourth (M2) transistors which are controlled to maintain and to inject charge to a DAC comprising the ADC; and
a biasing circuit that generates a voltage that is complementary to a temperature at which transistors comprising the CIC operate, the biasing voltage being applied to gate nodes of the first and second transistors and to a drain node of a fifth transistor (M10) that matches the first and second cascoded transistors, wherein the fifth transistor drain node is connected to the gate nodes of the first and second transistors.