US 12,413,235 B2
Digitally controlled delay line gain calibration using error injection
Ahmed Safwat Mohamed Aboelenein Elmallah, San Jose, CA (US); Amr Tarek Ahmed Abdelrazik Khashaba, San Jose, CA (US); Mohammed Mohsen Abdulsalam Abdullatif, San Jose, CA (US); and Tamer Mohammed Ali, San Jose, CA (US)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MediaTek Inc., Hsinchu (TW)
Filed on Oct. 23, 2023, as Appl. No. 18/492,518.
Claims priority of provisional application 63/383,923, filed on Nov. 16, 2022.
Prior Publication US 2024/0162907 A1, May 16, 2024
Int. Cl. H03L 7/183 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/183 (2013.01) [H03L 7/099 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for calibrating a phase-locked loop, comprising:
a digitally controlled delay line (DCDL) with a DCDL output and configured to:
receive a clock signal to be output from a voltage-controlled oscillator; and
delay the clock signal to generate a first delayed clock signal;
an error injection circuit with a first error injection input and a second error injection input, the first error injection input coupled to the DCDL output; and
a phase controller with a phase controller output coupled to the second error injection input, the phase controller configured to, in response to a pseudorandom binary sequence signal, instruct the error injection circuit to generate a second delayed clock signal based on a delay of the first delayed clock signal.