US 12,413,234 B2
Phase locked loop circuit and semiconductor device including the same
Kyung Min Lee, Suwon-si (KR); Gyu Sik Kim, Suwon-si (KR); Seung Jin Kim, Suwon-si (KR); and Jae Hong Jung, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 13, 2023, as Appl. No. 18/466,438.
Claims priority of application No. 10-2022-0116941 (KR), filed on Sep. 16, 2022; and application No. 10-2022-0146248 (KR), filed on Nov. 4, 2022.
Prior Publication US 2024/0106441 A1, Mar. 28, 2024
Int. Cl. H03L 7/093 (2006.01); G05F 3/26 (2006.01); H03L 1/00 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/093 (2013.01) [G05F 3/262 (2013.01); H03L 1/00 (2013.01); H03L 7/0995 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A phase locked loop circuit comprising:
a reference current generator configured to
generate a summed compensation current in which at least one of a process change, a temperature change or a power supply voltage change are compensated and
output the summed compensation current as a reference current;
a current digital-to-analog converter configured to convert the reference current into a control current in accordance with a digital code; and
a voltage control oscillator configured to generate a signal based on the control current,
wherein the summed compensation current is based on weighted-averaging a first type compensation current and a second type compensation current in response to at least one of the process change, the temperature change or the power supply voltage change.