| CPC H03K 21/38 (2013.01) [H03K 21/10 (2013.01)] | 10 Claims |

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1. A 4-bit synchronous counter integrated circuit (IC), comprising:
four binary output pins configured to output a 4-bit count representing the number of input triggers;
a clock input pin configured to increment the count on a rising edge trigger;
a clear (CLR) input pin configured to reset the output to zero when a LOW signal is applied;
a ripple carry-out (RCO) output pin configured to indicate when the counter output reaches a maximum binary count (16 counts);
a load input pin configured to load a user-defined 4-bit starting value from data inputs (A, B, C, D) into the counter on the next clock pulse; and
an active-low output pin (C10) configured to transition from HIGH to LOW when the count exceeds a single decimal digit.
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