| CPC H03K 19/0016 (2013.01) [H03K 3/356121 (2013.01); H03K 19/018521 (2013.01); H10D 89/10 (2025.01)] | 20 Claims |
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1. A semiconductor device comprising:
a first layer including a first semiconductor substrate, a plurality of first standard cell regions in the first semiconductor substrate, a plurality of first standard cells disposed in the plurality of first standard cell regions, and a plurality of first wiring patterns connected to the plurality of first standard cells; and
a second layer including a second semiconductor substrate, a plurality of second standard cell regions in the second semiconductor substrate, a plurality of second standard cells disposed in the plurality of second standard cell regions, and a plurality of second wiring patterns connected to the plurality of second standard cells, the second layer being stacked with the first layer in a vertical direction perpendicular to an upper surface of the first semiconductor substrate,
wherein the plurality of first standard cells comprise first combinational logic circuits,
wherein the plurality of second standard cells are electrically connected to the plurality of first standard cells and comprise sequential logic circuits, a clock gate circuit, and second combinational logic circuits,
wherein the plurality of second standard cells further comprise at least one of a power gate circuit or a level shifter circuit,
wherein the plurality of second wiring patterns comprise a transfer path for transmitting at least one of a scan signal or a scan enable signal to the sequential logic circuits included in the second layer, and
wherein at least one of the second combinational logic circuits is connected to the transfer path.
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