US 12,413,219 B2
Differential comparator circuit
Laurent Simony, Grenoble (FR)
Assigned to STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed on Dec. 15, 2023, as Appl. No. 18/541,324.
Claims priority of application No. 22306981 (EP), filed on Dec. 21, 2022.
Prior Publication US 2024/0213972 A1, Jun. 27, 2024
Int. Cl. H03K 5/24 (2006.01); H03M 1/56 (2006.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01)
CPC H03K 5/2481 (2013.01) [H04N 25/772 (2023.01); H04N 25/778 (2023.01); H03M 1/56 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An electronic circuit comprising a differential comparator circuit, the differential comparator circuit comprising:
a voltage amplifier of negative gain configured to receive an analog input signal and to generate an inverted analog input signal, wherein the analog input signal and the inverted analog input signal form differential analog input signals; and
a comparator input circuit comprising:
a first capacitive divider configured to generate a first signal as an average of the analog input signal and a first ramp signal; and
a second capacitive divider configured to generate a second signal as an average of the inverted analog input signal and a second ramp signal, wherein the first and second ramp signals are differential ramp signals;
wherein the differential comparator circuit is configured to compare the first signal with the second signal in order to generate a signal transition having a timing based on the analog input signal.