| CPC H03K 5/1565 (2013.01) [H03K 3/037 (2013.01); H03K 5/133 (2013.01)] | 16 Claims |
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1. A circuit portion comprising:
a signal generator, clocked by a clock signal, for generating an alternating logic signal comprising a repeated sequence of alternating logic transitions;
a circuit sub-portion which introduces a delay to the alternating logic signal;
an edge-travel detector, configured to sample the delayed alternating logic signal and to output an edge-travel signal representative of a timing of a logic transition in the alternating logic signal with respect to the clock signal; and
a mask block, configured to:
receive a mask signal representative of a candidate timing or a plurality of candidate timings of the logic transition with respect to the clock signal, wherein the mask signal comprises a plurality of bit positions, each bit position corresponding to a portion of the period of the clock signal;
compare the mask signal with the edge-travel signal to determine whether the timing of the logic transition matches the candidate timing or one of the plurality of candidate timings; and
output a comparison signal that is dependent on whether the timing of the logic transition matches the candidate timing or one of the plurality of candidate timings.
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