US 12,413,213 B1
Efficient clocking structures for high-speed systems using hybrid digital delay lanes
Jitendra Kumar Yadav, Bengaluru (IN); Sachin Ramesh Gugwad, Karnataka (IN); Hari Anand Ravi, Karnataka (IN); and Hajee Mohammed Shuaeb Fazeel, Bengaluru (IN)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Aug. 29, 2023, as Appl. No. 18/457,476.
Int. Cl. H03K 5/06 (2006.01); H03K 19/003 (2006.01); H03K 19/173 (2006.01)
CPC H03K 5/06 (2013.01) [H03K 19/00384 (2013.01); H03K 19/1737 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A high-speed clocking circuit, comprising:
a single path digitally controlled coarse delay line including multiple stages, wherein each of the multiple stages includes a plurality of inverters and a logic gate electrically connected in series that are configured to enable a forward path of the single path digitally controlled coarse delay line prior to disabling a return path of the single path digitally controlled coarse delay line to minimize glitching.