US 12,413,189 B2
Methods and devices for increased efficiency in linear power amplifier
Ali Azam, Hillsboro, OR (US); Wayne Ballantyne, Chandler, AZ (US); and LiChung Chang, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,019.
Prior Publication US 2022/0416735 A1, Dec. 29, 2022
Int. Cl. H03F 3/24 (2006.01); H03F 1/02 (2006.01); H03F 1/32 (2006.01); H03F 3/72 (2006.01)
CPC H03F 3/24 (2013.01) [H03F 1/0277 (2013.01); H03F 1/32 (2013.01); H03F 1/3211 (2013.01); H03F 3/72 (2013.01); H03F 2200/102 (2013.01); H03F 2200/321 (2013.01); H03F 2200/451 (2013.01); H03F 2200/465 (2013.01); H03F 2201/3215 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A power amplifier circuit comprising:
a plurality of analog power amplifiers configured to generate output signal power; and
at least one processor configured to:
select a highest output signal power;
determine an input signal power of a modulated signal, wherein the input signal power is based on a plurality of input signal user data symbols, wherein the plurality of input signal user data symbols include one or more resource blocks, wherein the input signal power is based on a count of the resource blocks in the plurality of input signal user data symbols, wherein the modulated signal comprises the plurality of input signal user data symbols;
determine an output signal power based on the input signal power;
compare the output signal power and the highest output signal power;
enable a power headroom; and
disable a subset of the plurality of analog power amplifiers based on the comparison, wherein a remainder of the plurality of analog power amplifiers are configured to generate the output signal power, wherein the output signal power includes the power headroom.