US 12,413,136 B2
Hybrid power transistor apparatus and control method
Chuan Ni, Plano, TX (US)
Assigned to LEN TECH Inc., Plano, TX (US)
Filed by LEN TECH Inc., Plano, TX (US)
Filed on Mar. 17, 2023, as Appl. No. 18/185,408.
Prior Publication US 2024/0313631 A1, Sep. 19, 2024
Int. Cl. H02M 1/44 (2007.01); H02M 1/00 (2006.01); H02M 1/08 (2006.01); H02M 1/088 (2006.01); H02M 3/158 (2006.01); H03K 17/16 (2006.01)
CPC H02M 1/08 (2013.01) [H02M 1/0048 (2021.05); H02M 1/088 (2013.01); H02M 1/44 (2013.01); H02M 3/158 (2013.01); H03K 17/16 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method comprising:
turning off a first switching element of a low-side switch;
with a first delay after turning off the first switching element of the low-side switch, turning off a second switching element of the low-side switch at a first time instant;
turning on a second switching element of a high-side switch at the first time instant; and
with a second delay after turning on the second switching element of the high-side switch, turning on a first switching element of the high-side switch, wherein gate drive signals of the first switching element of the low-side switch, the second switching element of the low-side switch, the second switching element of the high-side switch and the first switching element of the high-side switch are configured such that during a turn-on process of the high-side switch, a large on-resistance is connected between a parasitic inductor and a parasitic capacitor to damp an LC oscillation caused by the parasitic inductor and the parasitic capacitor.