US 12,412,876 B2
Semiconductor package
Kazuhito Tanaka, Shiga (JP)
Assigned to PANASONIC AUTOMOTIVE SYSTEMS CO., LTD., Kanagawa (JP)
Filed by Panasonic Intellectual Property Management Co., Ltd., Osaka (JP)
Filed on Jan. 31, 2023, as Appl. No. 18/162,489.
Claims priority of application No. 2022-018028 (JP), filed on Feb. 8, 2022.
Prior Publication US 2023/0253382 A1, Aug. 10, 2023
Int. Cl. H01L 25/16 (2023.01); H01L 23/00 (2006.01)
CPC H01L 25/16 (2013.01) [H01L 24/48 (2013.01); H01L 2224/4814 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19107 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a plurality of semiconductor chips that includes a system on chip (SoC) in which a plurality of integrated circuits including a processor core and a microcomputer are integrated on a single chip;
a power management integrated circuit (IC) for performing power management on the plurality of semiconductor chips;
a plurality of shunt resistors each of which is mounted in series on a different one of power wires connecting the power management IC and the plurality of semiconductor chips;
two output terminals; and
a single selector that outputs voltages at both ends of a shunt resistor to an outside via the two output terminals, the shunt resistor being selected from among the plurality of shunt resistors,
wherein the power management IC, the plurality of semiconductor chips, the plurality of shunt resistors, and the single selector are mounted inside a single package.