| CPC H01L 25/16 (2013.01) [H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/48228 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1438 (2013.01)] | 20 Claims |
|
1. A semiconductor package, comprising:
a package substrate including a passive element region, a peripheral region adjacent to the passive element region, and a remaining region;
a first passive element on a non-conductive upper surface of the package substrate in the passive element region;
a passive element connecting member connecting the first passive element to the package substrate;
a first semiconductor chip on a non-conductive upper surface of the package substrate in the remaining region; and
a sealing portion covering the package substrate, the first passive element, and the first semiconductor chip,
wherein the peripheral region includes a first sub-region on a first side of the first passive element, a second sub-region on a second side opposite the first side of the first passive element, a third sub-region on a third side of the first passive element, and a fourth sub-region on a fourth side opposite the third side of the first passive element,
wherein a roughness of a non-conductive upper surface of the package substrate in at least one of the first sub-region to the fourth sub-region is greater than a roughness of the non-conductive upper surface of the package substrate in the remaining region, and
wherein the first semiconductor chip overlaps the remaining region in a plan view.
|