US 12,412,871 B2
Semiconductor package utilizing a hybrid bonding process and method of manufacturing the same
Jihoon Kim, Cheonan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 23, 2023, as Appl. No. 18/518,591.
Application 18/518,591 is a continuation of application No. 17/367,005, filed on Jul. 2, 2021, granted, now 11,855,044.
Claims priority of application No. 10-2020-0151642 (KR), filed on Nov. 13, 2020.
Prior Publication US 2024/0088105 A1, Mar. 14, 2024
Int. Cl. H01L 25/065 (2023.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/3107 (2013.01); H01L 23/481 (2013.01); H01L 2225/06517 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor package, the method comprising:
forming upwardly protruding peripheral regions on an upper surface of a wafer, the wafer including a plurality of first semiconductor chips;
forming bonding regions on the upper surface of the wafer by forming a groove at the upwardly protruding peripheral regions;
hybrid-bonding a plurality of second semiconductor chips, each of which has an area larger than an area of each of the bonding regions, to the bonding regions to form an overhang at an edge portion of each of the second semiconductor chips, the overhang spaced apart from a bottom surface of the groove; and
cutting the wafer along the peripheral regions.