US 12,412,870 B2
Semiconductor memory device and method of manufacturing the same
Shinya Kobayashi, Taito (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jul. 11, 2022, as Appl. No. 17/811,654.
Claims priority of application No. 2021-205592 (JP), filed on Dec. 17, 2021.
Prior Publication US 2023/0197686 A1, Jun. 22, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 21/66 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 22/20 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first memory device and a second memory device arranged in a first direction; and
a plurality of first bump electrodes disposed between the first memory device and the second memory device, wherein
each of the first memory device and the second memory device includes:
a first chip including a memory cell array and a plurality of first electrodes;
a second chip including a peripheral circuit and a plurality of second electrodes; and
a plurality of second bump electrodes disposed between the first chip and the second chip,
the first direction is a thickness direction of the first memory device and the second memory device,
at least one of the plurality of first bump electrodes electrically connects at least one of the plurality of first electrodes included in the first memory device to at least one of the plurality of second electrodes included in the second memory device,
in the first memory device and the second memory device, at least one of the plurality of second bump electrodes electrically connects the memory cell array to the peripheral circuit,
the peripheral circuit of the first memory device is configured to be able to control the memory cell array of the first memory device, and
at least one of the plurality of second bump electrodes of the first memory device is disposed between the peripheral circuit of the first memory device and the memory cell array of the first memory device, and connects the peripheral circuit of the first memory device to the memory cell array of the first memory device in the first direction.