US 12,412,867 B2
Integrated fan-out package and manufacturing method thereof
Jhih-Yu Wang, New Taipei (TW); Hung-Jui Kuo, Hsinchu (TW); Yu-Hsiang Hu, Hsinchu (TW); Sih-Hao Liao, New Taipei (TW); and Yung-Chi Chu, Kaohsiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 26, 2023, as Appl. No. 18/396,575.
Application 18/396,575 is a continuation of application No. 17/465,872, filed on Sep. 3, 2021, granted, now 11,894,336.
Application 17/465,872 is a continuation of application No. 16/009,211, filed on Jun. 15, 2018, granted, now 11,114,407, issued on Sep. 7, 2021.
Prior Publication US 2024/0186283 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 23/544 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/82 (2013.01) [H01L 23/544 (2013.01); H01L 24/02 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 25/0655 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24155 (2013.01); H01L 2224/25171 (2013.01); H01L 2224/82106 (2013.01); H01L 2224/82132 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated fan-out (InFO) package, comprising:
a die;
an encapsulant laterally encapsulating the die; and
a redistribution structure disposed on the encapsulant, wherein the redistribution structure comprises a plurality of routing patterns and a plurality of alignment marks, the plurality of routing patterns is electrically connected to the die, the plurality of alignment marks surrounds the plurality of routing patterns, the plurality of alignment marks is electrically insulated from the die and the plurality of routing patterns, at least one of the plurality of alignment marks is in physical contact with the encapsulant, and the plurality of alignment marks located at different level heights is arranged in a non-overlapping manner vertically.