US 12,412,859 B2
Via wiring formation substrate, manufacturing method for via wiring formation substrate, and semiconductor device mounting component
Hiroyuki Kurihara, Tokyo (JP)
Assigned to SAN-EI KAGAKU CO., LTD., Tokyo (JP)
Appl. No. 17/294,285
Filed by SAN-EI KAGAKU CO., LTD., Tokyo (JP)
PCT Filed Nov. 15, 2019, PCT No. PCT/JP2019/044922
§ 371(c)(1), (2) Date May 14, 2021,
PCT Pub. No. WO2020/101022, PCT Pub. Date May 22, 2020.
Claims priority of application No. 2018-215049 (JP), filed on Nov. 15, 2018; application No. 2018-215050 (JP), filed on Nov. 15, 2018; and application No. 2019-164926 (JP), filed on Sep. 10, 2019.
Prior Publication US 2021/0407950 A1, Dec. 30, 2021
Int. Cl. H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 24/19 (2013.01) [H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H01L 24/24 (2013.01); H01L 2224/2402 (2013.01); H01L 2224/24225 (2013.01); H01L 2224/245 (2013.01); H01L 2924/0665 (2013.01); H01L 2924/15747 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A via wiring formation substrate for mounting at least one semiconductor chip, the via wiring formation substrate comprising
a support substrate,
a releasable adhesive layer provided on the support substrate,
a first insulating layer provided on the releasable adhesive layer, and
a second insulating layer laminated on the first insulating layer,
wherein the first insulating layer and the second insulating layer are provided with a plurality of via wiring formation vias, the via wiring formation vias enabling formation of via wirings which respectively correspond to a plurality of connection terminals of the semiconductor chip and which respectively are configured to connect the plurality of connection terminals, such that the via wiring formation vias penetrate only through the first insulating layer and the second insulating layer without misalignment; and
the total thickness of the first insulating layer and the second insulating layer is selected from a range of 15 μm to 70 μm,
the second insulating layer is configured to be brought into direct contact with an active surface of a semiconductor chip to be mounted, and
the via wiring formation vias are straight vias having a diameter of 15 μm to 70 μm and positional accuracies of ±5 μm or less.