US 12,412,837 B2
Interconnect structure including topological material
Meng-Pei Lu, Hsinchu (TW); Shin-Yi Yang, Hsinchu (TW); Cian-Yu Chen, Hsinchu (TW); Yun-Chi Chiang, Hsinchu (TW); and Ming-Han Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Apr. 8, 2022, as Appl. No. 17/716,485.
Prior Publication US 2023/0326857 A1, Oct. 12, 2023
Int. Cl. H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/53271 (2013.01) [H01L 21/76807 (2013.01); H01L 21/7682 (2013.01); H01L 21/76885 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53209 (2013.01); H01L 23/53295 (2013.01); H01L 21/76831 (2013.01); H01L 21/76846 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate; and
an interconnect layer disposed over the substrate and including an interconnect structure, the interconnect structure including a topological material,
wherein
the interconnect structure includes a first conductive line and a second conductive line which are spaced apart from each other to form a trench between the first conductive line and the second conductive line and which include the topological material;
the interconnect layer further includes a first dielectric liner which is disposed in the trench and between the first conductive line and the second conductive line and which conformally covers a lateral wall of each of the first conductive line and the second conductive line, and a capping layer disposed in the trench; and
the first dielectric liner cooperates with the capping layer to define an air gap.