US 12,412,833 B2
TopVia interconnect with enlarged via top
Lawrence A. Clevenger, Saratoga Springs, NY (US); Chen Zhang, Guilderland, NY (US); Brent Anderson, Jericho, VT (US); and Nicholas Anthony Lanzillo, Wynantskill, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 24, 2021, as Appl. No. 17/304,674.
Prior Publication US 2022/0415790 A1, Dec. 29, 2022
Int. Cl. H01L 23/528 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/5283 (2013.01) [H01L 21/31111 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor interconnect structure, comprising:
a first dielectric layer, the first dielectric layer having a top surface;
a bottom metal line in the first dielectric layer, the bottom metal line having a top surface below the top surface of the first dielectric layer;
a second dielectric layer above the top surface of the bottom metal line and against respective sidewalls of the first dielectric layer;
a via etched through the second dielectric layer and resulting in etched surfaces of the second dielectric layer, wherein the via exposes a portion of the top surface of the bottom metal line, respective portions of the sidewalls of the first dielectric layer, and a portion of the top surface of the first dielectric layer; and
a metal stud in the via that is in contact with the portion of the top surface of the bottom metal line, wherein the metal stud extends over the exposed portion of the top surface of the first dielectric layer, and wherein the metal stud comprises respective surfaces that are coplanar with the etched surfaces of the second dielectric layer.