| CPC H01L 23/5226 (2013.01) [H01L 21/762 (2013.01); H01L 21/76804 (2013.01); H01L 21/76883 (2013.01); H10D 30/60 (2025.01); H10D 30/62 (2025.01); H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 62/151 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01); H10D 86/011 (2025.01); H01L 21/76831 (2013.01); H01L 23/5286 (2013.01); H01L 2924/13091 (2013.01); H10D 84/85 (2025.01)] | 18 Claims |

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1. A semiconductor device comprising:
a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions;
a gate cut region at cell boundaries between the first and second S/D epitaxial regions;
a dielectric liner and a dielectric core formed in the gate cut region;
a backside power rail (BPR) and a backside power distribution network (BSPDN);
a power via passing through the dielectric core and connecting to the BPR and the BSPDN;
first metal contacts formed in contact with the first and second S/D epitaxial regions; and
a via to backside power rail (VBPR) contact,
wherein the dielectric liner separates the power via from the first S/D epitaxial region, and a portion of the dielectric liner is removed on only one side of the power via and the VBPR contact is formed in a location where this portion of the dielectric liner is removed.
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