US 12,412,827 B2
Semiconductor die package with conductive line crack prevention design
Ya-Huei Lee, Zhunan Township, Miaoli County (TW); Shu-Shen Yeh, Taoyuan (TW); Kuo-Ching Hsu, Taipei (TW); Shyue-Ter Leu, Hsinchu (TW); Po-Yao Lin, Zhudong Township, Hsinchu County (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 20, 2023, as Appl. No. 18/513,866.
Application 18/513,866 is a continuation of application No. 17/377,620, filed on Jul. 16, 2021, granted, now 11,854,956.
Prior Publication US 2024/0096778 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/1016 (2013.01); H01L 2924/20645 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor die package, comprising:
a semiconductor die having a corner; and
a package substrate supporting and electrically connected to the semiconductor die, wherein the package substrate comprises a plurality of conductive lines, and one of the conductive lines under the corner comprises:
a first line segment; and
a second line segment connected to the first line segment, wherein the first line segment is linear and extends in a first direction, and the second line segment is non-linear and has a varying extension direction.