US 12,412,824 B2
Semiconductor packages and methods of forming the same
Yeongbeom Ko, Suwon-si (KR); Junyun Kweon, Suwon-si (KR); Wooju Kim, Suwon-si (KR); Heejae Nam, Suwon-si (KR); Haemin Park, Suwon-si (KR); and Junggeun Shin, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 13, 2023, as Appl. No. 18/154,261.
Claims priority of application No. 10-2022-0076929 (KR), filed on Jun. 23, 2022.
Prior Publication US 2023/0420352 A1, Dec. 28, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H10B 80/00 (2023.01)
CPC H01L 23/49833 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3135 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H10B 80/00 (2023.02); H01L 24/48 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/95001 (2013.01); H01L 2224/96 (2013.01); H01L 2224/97 (2013.01); H01L 2924/182 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first redistribution structure including a first redistribution via;
a first package that is on an upper surface of the first redistribution structure and comprises:
a package substrate including a first pad;
a first semiconductor chip on the package substrate; and
a first encapsulant on the first semiconductor chip;
a second encapsulant on the first package;
a second redistribution structure that is on a lower surface of the first redistribution structure and comprises a second redistribution via;
a second semiconductor chip that is between the first redistribution structure and the second redistribution structure and comprises a connection pad;
a vertical connection structure that is between the first redistribution structure and the second redistribution structure; and
a third encapsulant on the second semiconductor chip and the vertical connection structure,
wherein the vertical connection structure is electrically connected to the first redistribution via and the second redistribution via,
wherein the connection pad is electrically connected to the second redistribution via,
wherein the first redistribution via is electrically connected to the first pad, and
wherein an upper surface of the first encapsulant is exposed from the second encapsulant.