US 12,412,821 B2
Semiconductor package
Yun Seok Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 13, 2023, as Appl. No. 18/538,458.
Application 18/538,458 is a continuation of application No. 17/181,116, filed on Feb. 22, 2021, granted, now 11,887,919.
Claims priority of application No. 10-2020-0085590 (KR), filed on Jul. 10, 2020.
Prior Publication US 2024/0113003 A1, Apr. 4, 2024
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/367 (2006.01)
CPC H01L 23/49827 (2013.01) [H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 23/49811 (2013.01); H01L 23/49894 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 23/147 (2013.01); H01L 23/3675 (2013.01); H01L 24/73 (2013.01); H01L 2224/73204 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a lower semiconductor chip having a first surface and a second surface which are opposite to each other;
an upper semiconductor chip on the first surface of the lower semiconductor chip;
a lower substrate on the second surface of the lower semiconductor chip;
a mold layer between the second surface of the lower semiconductor chip and the lower substrate;
a first through-electrode penetrating the lower semiconductor chip;
a second through-electrode penetrating the mold layer; and
a bump between the mold layer and the lower substrate,
wherein the first through-electrode is connected to the second through-electrode, the second through-electrode is connected to the bump, and the bump is connected to the lower substrate,
wherein the mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the lower semiconductor chip, and
wherein a thickness in a first direction of the mold layer is less than a thickness in the first direction of the lower semiconductor chip, and the first direction is perpendicular to the first surface of the lower semiconductor chip.