US 12,412,815 B2
Semiconductor package and method of manufacturing a semiconductor package
Thomas Beer, Mauerstetten (DE); Daniel Hoelzl, Unterhaching (DE); Ralf Otremba, Kaufbeuren (DE); and Klaus Schiess, Allensbach (DE)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Sep. 20, 2021, as Appl. No. 17/479,095.
Claims priority of application No. 20198813 (EP), filed on Sep. 28, 2020.
Prior Publication US 2022/0102253 A1, Mar. 31, 2022
Int. Cl. H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 25/04 (2023.01)
CPC H01L 23/49575 (2013.01) [H01L 23/298 (2013.01); H01L 23/49513 (2013.01); H01L 24/29 (2013.01); H01L 24/45 (2013.01); H01L 25/04 (2013.01); H01L 2224/29 (2013.01); H01L 2224/45 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a leadframe comprising first, second and third die pads and a plurality of individual leads that are spaced apart from the first, second and third die pads and one another, wherein the first, second and third die pads each have an upper surface and a lower surface and are laterally spaced part from one another;
a mold compound, wherein the upper surface of the first, second and third die pads is arranged within the mold compound and the lower surface of the second die pad is exposed from the mold compound and spaced apart from a side face of the mold compound by a distance that is greater than the length of the individual leads;
a first power semiconductor device;
a second power semiconductor device; and
a control semiconductor device,
wherein the individual leads each have an upper surface having a length that extends substantially perpendicularly to the side face of the mold compound,
wherein the first power semiconductor device is mounted on the upper surface of the first die pad,
wherein a drain pad of the first power semiconductor device is electrically coupled to the second die pad by one or more first connectors that extend between the first power device and the upper surface of the second die pad,
wherein the upper surface of the second die pad is either occupied by the one or more first connectors or in direct contact with the mold compound,
wherein the second die pad remains unoccupied by a semiconductor die or semiconductor device and is used solely to provide a portion of an internal electrically conductive redistribution structure.