US 12,412,811 B2
Split via structure for semiconductor device packaging
Hong Wan Ng, Singapore (SG); Seng Kim Ye, Singapore (SG); Kelvin Tan Aik Boo, Singapore (SG); Ling Pan, Singapore (SG); and See Hiong Leow, Singapore (SG)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 23, 2022, as Appl. No. 17/894,102.
Prior Publication US 2024/0071869 A1, Feb. 29, 2024
Int. Cl. H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76879 (2013.01); H01L 21/76898 (2013.01); H01L 23/5283 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device assembly, comprising:
a substrate;
a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and
a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint,
wherein the first via land and the second via land are disposed entirely within a circular region having the first radius of curvature, and
wherein the first via land and the second via land are symmetric in the circular region and isolated by a first gap.