US 12,412,804 B2
Semiconductor structure with improved heat dissipation
Cheng-Chin Lee, Taipei (TW); Shau-Lin Shue, Hsinchu (TW); Shao-Kuan Lee, Kaohsiung (TW); Hsiao-Kang Chang, Hsinchu (TW); Cherng-Shiaw Tsai, New Taipei (TW); Kai-Fang Cheng, Taoyuan (TW); Hsin-Yen Huang, New Taipei (TW); Ming-Hsien Lin, Hsinchu County (TW); Chuan-Pu Chou, Hsinchu County (TW); Hsin-Ping Chen, Hsinchu County (TW); Chia-Tien Wu, Taichung (TW); and Kuang-Wei Yang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 14, 2022, as Appl. No. 17/693,668.
Prior Publication US 2023/0290705 A1, Sep. 14, 2023
Int. Cl. H01L 23/373 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 30/62 (2025.01); H10D 84/83 (2025.01)
CPC H01L 23/3738 (2013.01) [H01L 23/3732 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10D 30/6211 (2025.01); H10D 84/834 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a device region formed over the substrate;
an interconnect structure formed over the device region;
a first passivation layer formed over the interconnect structure;
a metal pad formed over and extending into the first passivation layer;
a second passivation layer formed over the first passivation layer, wherein the second passivation layer comprises a thermal conductive material, and a thermal conductivity of the thermal conductive material is higher than 4 W/mK;
a barrier layer between the metal pad and the first passivation layer; and
an anti-reflection layer between the metal pad and the second passivation layer.