US 12,412,799 B2
Integrated circuit package and method
Chen-Hua Yu, Hsinchu (TW); Wei Ling Chang, Hsinchu (TW); Chuei-Tang Wang, Taichung (TW); Fong-Yuan Chang, Hsinchu (TW); and Chieh-Yen Chen, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/874,782.
Application 17/874,782 is a division of application No. 16/882,132, filed on May 22, 2020, granted, now 11,532,533.
Claims priority of provisional application 62/916,954, filed on Oct. 18, 2019.
Prior Publication US 2022/0359333 A1, Nov. 10, 2022
Int. Cl. H01L 23/31 (2006.01); H01L 21/02 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/3185 (2013.01) [H01L 21/02074 (2013.01); H01L 23/3192 (2013.01); H01L 24/02 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a processor die comprising circuit blocks, the circuit blocks comprising active devices of a first technology node;
a power gating die comprising power semiconductor devices of a second technology node, a pitch between adjacent ones of the power semiconductor devices of the second technology node being larger than a pitch between adjacent ones of the active devices of the first technology node; and
a first redistribution structure comprising first metallization patterns, the first metallization patterns comprising power supply source lines and power supply ground lines, wherein a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.